1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device for detecting soft errors generated in a ring oscillator circuit or other such oscillators and preventing malfunction resulting from soft errors.
2. Description of Related Art
Along with recent miniaturization in a semiconductor process of a semiconductor device composed of field effect transistors such as MOSFETs, a transient error (soft error) resulting from radiation (for example, high-energy neutron radiation, thermal neutron radiation, and α radiation) has been recognized as a problem. As an example of the soft error, there is SEU (Single Event Upset) that logic inversion occurs due to charges accumulated in a node decrease due to charges resulting from radiation. In general, the occurrence of the SEU depends on a trade-off between an amount of charges accumulated in an information storage node (node voltage x node capacitance) and an amount of charges gathered to the information storage node (collected charge amount) out of the charges generated in a substrate due to radiation. The collected charge amount is generally proportional to an area (volume, to be exact) of the information storage node. As a result of experiments made by the inventors of the present invention, it is revealed that a smaller diffusion layer has a higher resistance to the SEU as long as a voltage level is constant. If a voltage decreases due to miniaturization, the decreasing rate is determined depending on a relation between the accumulated charge amount and the collected charge amount as mentioned above.
The SEU causes a problem of, for example, data inversion that data stored in a memory cell is different from the original data. To give a typical countermeasure against the SEU, a capacitor is added to the storage node or an ECC (Error Correction Code) is added to a circuit.
The memory cell can avoid the SEU by taking the above countermeasure. However, if this countermeasure is adopted against a SEU that occurs in a circuit transmitting a clock signal or the like, an operational speed is reduced or a chip area is considerably increased, so this countermeasure is inappropriate.
In contrast to the SEU (data inversion) of the memory cell, SET (Single Event Transient) is a signal transmission error resulting from a noise generated by radiation being emitted to a signal transmitting logic circuit (hereinafter referred to as “dynamic circuit” for convenience' sake).
Regarding the SET, it is reported by Norbert Seifert, et al. in “Frequency Dependent of Soft Error Rates for Sub-micron CMOS Technologies” that the SEU is more likely to occur in a circuit having more signal paths and higher operational frequency. This relation can be expressed as model expressions, Expressions 1 and 2:Pset∝f (f=operational frequency)  (1)Pset∝N (N=target signal path)  (2)where Pset represents an error occurrence rate.
That is, as an operational frequency of a semiconductor integrated circuit improves, the occurrence of the SET increases as understood from Expression 1. As miniaturization in the semiconductor process proceeds and a circuit is upsized, the occurrence of the SET increases as understood from Expression 2.
As a countermeasure against the SET, a technique of preventing the SET using a majority circuit or a coincidence circuit is described in Pitsini Mongkolkachit et al., “Design Technique for Mitigation of Alpha-Particle-Induced Single-Event Transients in Combinational Logic”. However, incorporating the majority circuit or coincidence circuit increases a circuit area, so there is a possibility that necessary functional parts cannot be embedded in a limited area.
In general, most blocks of the semiconductor integrated circuit have an active mode and a suspend mode. The SET is an error that occurs in the active mode. As understood from the above explanation, parts that are operating at high speeds all the time most need the measure for the SET. Examples of the parts include a ring oscillator circuit for generating an internal clock of the semiconductor integrated circuit. FIG. 7 shows an example of a conventional typical ring oscillator circuit.
In the ring oscillator circuit of FIG. 7, an odd number of inverter circuits are connected in series, and an output of the last inverter circuit is an input of the first inverter circuit. In the related art of FIG. 7, if n=7, 15 inverter circuits are connected. FIG. 8 is a timing chart of an operation of the ring oscillator. As shown in FIG. 8, if no soft error occurs, a 5-th circuit (point A), a 10-th circuit (point B), and a 15-th circuit (point C) show waveforms as indicated by the solid lines.
However, if soft errors occur in an output of the 10-th inverter circuit at time t1, and a signal that would be at High level under ordinary circumstances is changed to Low level, the circuit shows a waveform as indicated by dotted line from time t1 onward. That is, from time t1 onward, a phase of a waveform at each point advances relative to the waveform before time t1. The soft error is propagated. When the error reaches the output stage, a High-level period is increased before and after time t1 in FIG. 8, and a phase of an output waveform is shifted during this period. As a result, the output waveform is changed such that its phase advances. If the output waveform having the phase shift is input to other logic circuits, the circuits may cause a problem such as an error in reading data or an operational failure due to a timing difference.
Further, after the wave of the waveform changed by the soft errors propagates to all inverter circuits of the ring oscillator circuit, that is, after one cycle of the output waveform, relative phase differences between the inverter circuits become the original phase differences. Hence, the above problem does not occur.
Japanese Unexamined Patent Application Publication Nos. 2004-221697 and 2004-328843 disclose a technique of controlling an oscillating waveform of an oscillating circuit like the ring oscillator circuit. The circuit as disclosed in Japanese Unexamined Patent Application Publication No. 2004-221697 adjusts a control voltage of a voltage control oscillator to normalize oscillation of the oscillator when a oscillation stopped period is more than a predetermined period.
Further, the circuit as disclosed in Japanese Unexamined Patent Application Publication No. 2004-328843 controls an output signal of an oscillating circuit while comparing an output voltage with a reference voltage in a DC/DC converter for generating a predetermined voltage by use of a signal output from the oscillating circuit.
However, the circuits disclosed in Japanese Unexamined Patent Application Publication Nos. 2004-221697 and 2004-328843 detect a continuous waveform abnormality and thus cannot detect a waveform abnormality that occurs only once in a short period, such as soft errors.